#3077 - Principal Design Engineer (High Speed Clock and Timing Circuit Design)

Engineering, Sunnyvale, CA

Regular, Full-time

  Req# 3077

Primary Job Responsibilities:

Design and implement a high speed low jitter/skew/latency clock distribution/network/topology for a high performance processor, SOC, and other timing sensitive designs. Will act as the main contributor from concept (architecture/topology trade-off) to GDS2. (design/analyze/implement).. Duties will include hands-on architecture planning, floor planning for optimum performance and area, latency/skew/power/area trade-off, and detailed timing/noise analysis and closure. Will need to have in-depth knowledge of PLL and timing related circuitry as well as clock path and buffer optimization for optimum area efficiency and high speed operation. Will be responsible for developing implementation plans and schedules. Will guide, mentor, and instruct other engineers and custom layout personnel toward efficient completion of projects. Will contribute to methodology development and supervise tasks that reach outside of primary area of expertise.

Products are from one or more of the following: Embedded Power PC processors, network processors, or communication processors. Speed range of processors can be from 1 GHz to 3 GHz in 90nm/65nm/45nm technology.


Education Requirement or Equivalent:

BS, MS, or PhD in Electrical Engineering



Experience Requirement:

BS: 8 years; MS: 4 years; PhD: 2 years; or equivalent work experience in the field of CMOS processor design and. Must have completed designs on 3 or more chips that have been built in silicon and work. Must have resolved non-routine design issues or problems. Must have contributed methodology solutions and flows used by others.



Special Skills or Knowledge Required:

Required skills are in-depth understanding of the principles of Clock and PLL architectures as well as customized circuit design. Expert knowledge of high speed logic design techniques and physical implementation principals is a must. Proficiency in timing analysis tools such as Pathmill, Timemill, and Spice as well as expertise in mixed signal capture and simulation. Proficiency at programming in Perl, or C in the UNIX/Linux environment.