#3081 - SOC Architect

Engineering, Austin, TX

Regular, Full-time

Primary Job Responsibilities:

Our products include PowerPC processors (500MHz all the way to 2GHz) including multi-processor core technology, Queue manager, Traffic manager, GE, 10GE, SATA, SAS, PCIe, SRIO, many high speed serial links (6gbps, 10gbps), DDR2/DDR3 DRAM controller, low performance peripherals, on chip memory, AMBA AXI buses, IEEE 1588, NAT, TCP offload, On Chip Memory, security subsystem including Kazumi, AES, SHA, MD5, content inspection...many DMAC and bridges to interface different buses. These chips have many different clock domains also.



Education Requirement or Equivalent:

BSEE/MSEE or BSCE/MSCE 10-15 years of total experience, with at least 5 recent years of successive experience architecting and integrating complex SOCs /multi-purpose microprocessors PCI Express, USB, Ethernet, packet processing, Serdes & highspeed interfaces.


Experience Requirement:

This particular position involves architecting the next generation SOCs:
- Writing the chip architecture document
- Evaluating and selecting IPs
- Architecting clock distribution, PLL selection, clock generation, reset & intialization schemes.
-architecting the bridges
- Performing bus bandwidth and I/O bandwidth calculations
- Calculating buffer and queue sizes and depths
- Working with the system architecture group to come up with solutions for different customer requirements
- Working with the verification group to implement a comprehensive verification plan for the chips
- Cooperating with the s/w group in the development of drivers and s/w




-Defining I/O pin list.
Special Skills or Knowledge Required:

The position requires the individual to have experience in networking, networking protocols, PCI, high speed IO, industry standard buses and processors. Any knowledge of wireless protocols and IP would be a big plus. Knowledge and experience in communication and networking is a must. Experience in Verilog, C/C++ and scripting is a must.