Principal Design Engineer (Memory Interfaces, DDR2/3)

Engineering, Sunnyvale, CA

Regular, Full-time

 

Primary Job Responsibilities:
Job functions will include working with architects, design, verification, and validation in defining, implementing and bringing-up various high-speed memory controllers and interfaces. Candidate should be highly skilled and knowledgeable in the area of memory device architecture and interfaces for integration into complex SOCs, specifically DDR interfaces and DDR2/3 and future protocols. Additionally the candidate will participate on the JEDEC committee to keep AMCC ahead of competition on DDR technology and interfaces. The candidate will also work closely with the mixed signal group at AMCC to help define the DDR PHY architecture and timing and the interface between the memory controller and the PHY interface.


Education Requirement or Equivalent:

BSEE/MSEE/PhD.

Experience Requirement:

Candidate should have 8+ years of experience with design and micro-architecture of complex chips. Must have 3 years experience with DDR2, DDR3 controllers and physical interfaces. Must have experience with SoC architecture and design with standard SoC busses like AXI, AHB, PLB etc.


Special Skills or Knowledge Required:


Experience with other memory interfaces, such as RLDRAM, QDR, is highly desired. Good knowledge of Verilog required, SystemVerilog is desired. Must have experience with synthesis, timing, and simulation, lab bringup experience is desired.