#3192 - Principal Static Timing Engineer

Engineering, Austin, TX

Regular, Full-time

Primary Job Responsibilities:

Develop, script, run, and maintain a static timing sign-off flow using PrimeTime-SI. Designs are hierarchical with numerous clock domains, domain to domain interfaces, clock gating, PLLs, DLLs, synchronous and asynchronous clocks. The assignment includes running jobs, debugging constraints, and suggesting alternative solutions to some of the more challenging design closure issues.

Education Requirement or Equivalent:

BS, MS, or PhD in Electrical Engineering.

Experience Requirement:

BS: 8 years; MS: 4 years; PhD: 2 years; or equivalent work experience in the field of CMOS processor design. Must have completed designs on 3 or more chips that have been built in silicon and work. Must have resolved non-routine design issues or problems. Must have contributed methodology solutions and flows used by others.

Special Skills or Knowledge Required:

Required skills are in-depth knowledge of static timing requirements, constraints, and debug of PrimeTime-SI is required.

Proficiency in timing analysis tools such as PrimeTime-SI and Spice. Proficiency at programming in Perl, or C in the UNIX/Linux environment.