#3323 Full Chip Timing Analysis, Principle Engineer

Engineering, Austin, TX

Regular, Full-time

Primary Job Responsibilities:

In this principle level position, you would be responsible for generating chip level constraints, exceptions, and achieving timing closure for a complex SOC with many clock domains and high speed IO. You will have to work with different engineering teams/functions so team work, communication, and strong initiative will be required.



Education Requirement or Equivalent:

You MUST have hands-on design/methodology experience and EXPERTISE with STA, PrimeTime and PrimeTimeSI, timing constraints development. MUST be knowledgeable about floorplanning, routing, clock tree and DSM effects. Experience with DDR2/3, and knowledge of Perl and Tcl preferred.


Experience Requirement:

BSEE or MSEE (preferred)
Minimum of 8 yrs of design experience


Special Skills or Knowledge Required:

N/A